Tektronix BSA286C in United States
Location:
United States
Price:
$89,000 USD
Model:
BSA286C

Specifications

Condition:
used
Format:
NRZ
Display:
TFT touch screen 640 x 480 VGA
Division:
Test and Measurement
Polarity:
Normal or Inverted
Amplitude:
LVTTL (<0.5 V Low, >2.5 V High)
Connector:
APC-3.5 Planar Crown®
Impedance:
50 Ω
Interface:
BNC female, >1 kΩ impedance into 0 V
Threshold:
+1.2 V
Resolution:
100 fs
Interface 2:
SMA female
Interface 3:
50 Ω SMA female
Interface 4:
SMA female, >1 kΩ impedance into 0 V
Launch date:
Sep-2012
Logic family:
LVTTL (<0.5 V Low, >2.5 V High)
Configuration:
Differential
Output levels:
1000 mV nominal (0 V to 1 V low-high)
Pattern depth:
Pattern capture length up to 128 Mb
Max. data rate:
28.60 Gbps
Min. data rate:
1.00 Gbps
Trigger output:
Provides a pulse trigger to external test equipment
Data rate range:
1 - 28.6 Gb/s
Max. clock rate:
28.6 GHz
Output levels 2:
>300 mV amplitude, 650 mV offset
Transition time:
<500 ps
Hardware patterns:
Industry-standard Pseudo-random (PRBS) of the type 2
Maximum frequency:
<4000 markers/s recommended
Threshold presets:
LVPECL, LVDS, LVTTL, CML, ECL, SCFL
Threshold voltage:
–2 to +3.5 V
Minimum pulse width:
128 clock periods
Range above 1.1 ghz:
3 ns
Range up to 1.1 ghz:
30 ns
Threshold alignment:
Can auto-align to differential crossing point
Minimum pulse width 2:
128 serial clock periods
Max. prbs pattern(2n-1):
31
Maximum repetition rate:
512 serial clock periods
Ram pattern user defined:
128 bits to 128 Mb, 128-bit increments
Clock input configuration:
Single ended
Max nondestructable input:
–3 Vpeak, +4 Vpeak, applied to any connector
Maximum input signal swing:
2 Vp-p
Subcategory:
Telecom, datacom
Subcategory 2:
Bert, error analyzers

Description

Tektronix BSA286C-JMAP-LDA-PVU-SF-STR 28Gb/s BER Analyzer
Pattern Generation and Error Analysis, High-speed BER Measurements up to
28.6 Gb/s.
Integrated, Calibrated Stress Generation to Address the Stressed
Receiver Sensitivity and Clock Recovery Jitter Tolerance Test
Requirements for a Wide Range of Standards.
Jitter Tolerance Compliance Template Testing with Margin Testing.
Fast Input Rise Time / High Input Bandwidth Error Detector for Accurate
Signal Integrity Analysis.
Integrated Eye Diagram Analysis with BER Correlation.
Patented Error Location Analysis.
OPTS001 includes:
J-MAP = Jitter decomposition SW
LDA = Live data analysis SW
PVU = Pattern Vu Equalization Processing SW
PCISTR = Extended Stress Generation, requires STR.
STR = Stressed Signal Generation, Includes option ECC, MAP,PL,XSSC,JTOL
,SF
The BERTScope™ BSA Series Bit Error Rate Testers provide a new approach to signal integrity measurements of serial data systems. Perform bit error ratio detection more quickly, accurately, and thoroughly by bridging eye diagram analysis with BER pattern generation. The BERTScope BSA Series lets you easily isolate problematic bit and pattern sequences, then analyze further with seven types of advanced error analysis that deliver unprecedented statistical measurement depth.
Pattern generation and error analysis, highspeed BER Measurements up to 28.6 Gb/s
Integrated, calibrated stress generation to address the stressed receiver sensitivity and clock recovery jitter tolerance test requirements for a wide range of standards
Sinusoidal jitter to 100 MHz
Random jitter
Bounded, uncorrelated jitter
Sinusoidal interference
Spread spectrum clocking
PCIe 2.0 & 3.0 receiver testing
F/2 jitter generation for 8xFC and 10GBASE-KR testing
IEEE802.3ba & 32G fibre channel testing
Electrical stressed eye testing for
PCI Express
10/40/100 Gb Ethernet
SFP+/SFI
XFP/XFI
OIF/CEI
Fibre Channel (FC8, FC16, FC32)
SATA
USB 3.0
InfiniBand (SDR, QDR, FDR, EDR)
Integrated BER correlated eye diagram analysis with pass/fail masks for PCI Express, USB, SATA and other communications standards
Error location and BER contour analysis on PRBS 31 and other digital signals up to 28.6 GB/sec
Jitter tolerance compliance template testing with margin testing
Fast input rise time / high input bandwidth error detector for accurate signal integrity analysis
Physical layer test suite with mask testing, jitter peak, BER contour, and Q-factor analysis for comprehensive testing with standard or user-defined libraries of jitter tolerance templates
Integrated eye diagram analysis with BER correlation
Patented Error Location Analysis™ enables rapid understanding of your BER performance limitations and assesses deterministic versus random errors, performs detailed pattern-dependent error analysis, performs error burst analysis, or error-free interval analysis
Optional jitter map provides fast jitter decomposition, accurate stress calibration at the DUT input
Optional digital pre-emphasis processor prov