The MP1764C Error Detector is used in combination with the
Pulse Pattern Generator for 12.5G Bit Error Rate Testing to evaluate components and systems in conformity with ITU-T standards. Complicated searching for input thresholds or phase adjustments is simplified with the touch of a single key. These functions are ideally suited for the research and development of ultrahigh speed logic ICs and digital communication systems.
This is the only 12.5G BERT system with differential inputs and ¼ differential outputs required for SAN market device applications. In addition, this system supports 4.25G CDR for Fibre Channel applications.
MP1764D is a version of the MP1764C that includes options for Differential Input (option MP1763C-02) and Variable CDR (option MP1764C-03).
Wide frequence range covers STM-0/STS-1 to 10 GbE, STM-64/STS-192, OTU-2, and 4.25G Fibre Channel
Differential Input option supports high speed differential signals used by XAUI and SFI-4P2 4-lane devices
Variable CDR option supports bit rates from 62.5M to 11.1G plus 4.25G for Fibre Channel
Burst measurement capability is essential for circulating loop measurements
Auto-search function for setting optimum values of input threshold and phase setting by "one-touch" operation
Synchronization of 8 Mbits pattern is easily made within a short period of time (when in frame mode)
Errors are detected in intervals as short as 0.1 sec.
Zero wait time counter gate
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